发明名称 SYSTEM CLOCK OPTIMIZING METHOD FOR REDUCING POWER CONSUMPTION
摘要 A method for optimizing a system clock to reduce power consumption is provided to generate the optimized system clock autonomously in a multimedia playback system in real-time without performing lots of tests for calculating the optimized system clock for playing various kinds of multimedia data, and reduce the power consumption by applying the optimized system clock. Three reference quantities for checking data quantity stored to an output buffer are set up(ST10), and multimedia data is decoded and stored to the output buffer. The data quantity of the data stored in the output buffer and a data quantity changing rate are checked(ST30). A system clock frequency is decreased by a predetermined amount when the data quantity is bigger than the top reference quantity(ST100). The system clock frequency is increased by the predetermined amount when the data quantity is smaller than the bottom reference quantity(ST120). The system clock frequency is increased by the predetermined amount when the data quantity is smaller than the middle reference quantity and the data quantity is decreased faster than a predetermined changing rate by determining the data quantity changing rate(ST110).
申请公布号 KR100865406(B1) 申请公布日期 2008.10.24
申请号 KR20080020732 申请日期 2008.03.05
申请人 TELECHIPS INC. 发明人 LEE, JEONG YEOP
分类号 G06F1/32 主分类号 G06F1/32
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