发明名称 TWO FREQUENCY MATCHING CIRCUIT
摘要 <p>Connection topology of input terminals (2), elements (4a, 4b, 4c, 4d), and a load (5) employs a "seven segment display" applied to numerical display of electronic calculator or digital clock. When the input terminals (2) are assigned to the uppermost and lowermost segments out of three segments extending laterally in a seven segment display, and the load (5) is assigned to one remaining segment extending in the lateral direction, four remaining segments in the longitudinal direction correspond to the elements (4a, 4b, 4c, 4d). With such circuitry, total number of elements is decreased to 4 and low loss is achieved, and highly stable impedance matching is attained against impedance variation of the load (5) by eliminating the resonance circuit from the constituent circuit and reducing the scale of a ladder circuit.</p>
申请公布号 WO2008126386(A1) 申请公布日期 2008.10.23
申请号 WO2008JP00828 申请日期 2008.03.31
申请人 PANASONIC CORPORATION;SANGAWA, USHIO 发明人 SANGAWA, USHIO
分类号 H03H7/38;H04B1/04 主分类号 H03H7/38
代理机构 代理人
主权项
地址