| 摘要 |
Methods and apparatus are provided for magnetoresistive random access memory (MRAM) bits ( 52, 52 ') combined with associated drive or sense transistors ( 53, 141 ) to form an integrated MRAM array. The MRAM array has lower electrodes ( 602, 150, 160, 162 ) of the MRAM bits ( 52, 52 ') formed substantially directly on a source or drain region ( 56, 142, 152 - 2 ) of associated drive or sense transistors ( 53, 141 ), so that the intervening vias ( 302, 34, 36 ) and underlying interconnects layers ( 332, 35 ) of the prior art ( 20 ) can be eliminated. An interconnect layer ( 65 ) is provided above the MRAM bit ( 52, 52 ') and transistor ( 53, 141 ) combination ( 50, 125, 129, 133 ) for coupling upper electrodes ( 41, 164 ) of the MRAM bits ( 52, 52 ') and other electrodes ( 601, 58, 152 - 1, 152 - 3, 186 - 1, 186 - 3 ) of the transistors ( 53, 141 ) to other elements of the array. Because the lower electrodes ( 37, 602, 150, 160, 162 ) of the MRAM bits ( 52, 52 ') are formed in substantial contact with the source or drain regions ( 56, 142 - 2, 152 - 2 ) of the transistors ( 53, 141 ), a separate interconnect layer ( 33, 35 ) and/or via ( 302, 34 ) for that purpose is not needed. As a consequence, the MRAM array is more space and process efficient.
|
