发明名称 |
DIGITAL SIGNAL DECODING APPARATUS |
摘要 |
<p>In a bit stream syntax of sliced video compressed data which is video compressed data having a sliced structure, each sliced video compressed data has a slice header of each sliced video compressed data, the header multiplexing: a slice start code, a register reset flag indicating whether to reset a register value indicating the code word state of an arithmetic encoding process in the next transmission unit, the initial register value which is a register value at that moment so as to be used as a register value upon start of arithmetic encoding and decoding of the next transmission unit if the register reset flag indicates ~not to perform reset~.</p> |
申请公布号 |
CA2449924(C) |
申请公布日期 |
2008.06.17 |
申请号 |
CA20032449924 |
申请日期 |
2003.04.10 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
SEKIGUCHI, SHUNICHI;YAMADA, YOSHIHISA;ASAI, KOHTARO |
分类号 |
H03M7/40;G06T9/00;H04N7/24;H04N7/50;H04N7/52;H04N19/00;H04N19/105;H04N19/13;H04N19/174;H04N19/46;H04N19/51;H04N19/625;H04N19/70;H04N19/91 |
主分类号 |
H03M7/40 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|