| 摘要 |
A SigmaDelta modulator for producing a modulation signal for modulating a frequency division ratio of a comparison frequency divider of a PLL circuit. A plurality of integrators connected in series integrate an input signal and output overflow signals when the integrated value has exceeded a predetermined value. Differentiators transfer the overflow signals of the integrators. An adder multiplies predetermined coefficients by output signals output from the differentiators and adds the multiplied values. The absolute values of the predetermined coefficients of the adder are set to be less than the predetermined value. This setting decreases the modulation width of the modulation signal.
|
