| 摘要 |
<P>PROBLEM TO BE SOLVED: To reproduce clock without using a VCO circuit for generating clock. <P>SOLUTION: An audio reproduction circuit 40 is provided with a video clock VCK synchronizing with a transmission side video clock reproduced based on a frame synchronous signal generated based on a receiving stream. The audio reproduction circuit 40 comprises a PLL (Phase Locked Loop) circuit 44 for generating an audio master clock MCK by multiplying and frequency dividing the VCK, a circuit 42 for counting the number of MCK in one frame, and a period regulation circuit 41 for generating an audio bit clock BCK from a predetermined number of MCK. Based on the number of transmitted audio samples and the current MCK count, the period regulation circuit 41 regulates the period of BCK in units of MCK such that the clock corresponds with the number of samples. <P>COPYRIGHT: (C)2007,JPO&INPIT |
