发明名称 Method Of Assessing Potential For Charging Damage In Integrated Circuit Designs And Structures For Preventing Charging Damage
摘要 Disclosed is a method and circuit for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The method/circuit prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source/drain and gate as susceptible devices within a given region, and connecting a element across the source/drain and the gate of each of the susceptible devices such that the element is positioned within the region. Alternatively, the method/circuit provides for connecting compensating conductors to an element to eliminate potential charging damage.
申请公布号 US2006086984(A1) 申请公布日期 2006.04.27
申请号 US20060275482 申请日期 2006.01.09
申请人 发明人 HOOK TERENCE B.;ZIMMERMAN JEFFERY S.
分类号 H01L23/62 主分类号 H01L23/62
代理机构 代理人
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