发明名称 |
Content addressable memory with priority-biased error detection sequencing |
摘要 |
A content addressable memory (CAM) device having circuitry to generate a biased sequence of addresses. A first counter circuit increments an address value in response to a clock signal and resets the address value to a start address in response to a control signal. A second counter increments a limit value in response to a control signal. A compare circuit compares the address value and the limit value and, if the address value and the limit value have a predetermined relationship, asserts the control signal.
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申请公布号 |
US7043673(B1) |
申请公布日期 |
2006.05.09 |
申请号 |
US20010002713 |
申请日期 |
2001.11.01 |
申请人 |
NETLOGIC MICROSYSTEMS, INC. |
发明人 |
ICHIRIU MICHAEL E.;SRINIVASAN VARADARAJAN |
分类号 |
G11C29/00;G11C15/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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