发明名称 |
Memory array bit line coupling capacitor cancellation |
摘要 |
Capacitive coupling correction circuits are coupled between adjacent parallel dynamic (pre-charged) or static conductors. The capacitive coupling correction circuits effectively isolate a low voltage applied to a first conductor from a high pre-charged voltage stored on an adjacent second conductor (or vice versa). The adjacent parallel conductors can be bit lines of a memory cell. Each capacitive coupling correction circuit can include an inverter having an input terminal coupled to the first conductor, and an output terminal coupled to a first plate of a capacitor. A second plate of the capacitor is coupled to the second conductor. The capacitance of the capacitor is selected to be identical to a parasitic capacitance between the first and second conductors. As a result, there is a zero net voltage effect between the first and second conductors. The capacitive coupling correction circuits may be distributed along the length of the first and second conductors.
|
申请公布号 |
US7443747(B2) |
申请公布日期 |
2008.10.28 |
申请号 |
US20040997708 |
申请日期 |
2004.11.23 |
申请人 |
INTEGRATED DEVICE TECHNOLOGY, INC. |
发明人 |
LIEN CHUEN-DER;YEH TZONG-KWANG HENRY |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|