发明名称 |
PLL circuit and frequency setting circuit using the same |
摘要 |
Disclosed is a PLL circuit in which an AC signal with a predetermined frequency is supplied as an input signal to a phase shifter comprising an OTA and a capacitor, and a phase comparator that receives the input signal to the phase shifter and an output signal from the phase shifter outputs a signal corresponding to a phase difference between the input signals. Control is performed so that the phase difference given by the phase shifter becomes a constant value by changing a transconductance (gm) of at the OTA constituting the phase shifter, using an output voltage of an amplifier for amplifying a DC voltage of the output signal of the phase comparator as a control signal.
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申请公布号 |
US7443214(B2) |
申请公布日期 |
2008.10.28 |
申请号 |
US20050126294 |
申请日期 |
2005.05.11 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
KIMURA KATSUJI |
分类号 |
H03H11/04;H03L7/06;H03H11/12;H03L7/081;H03L7/085;H03L7/093 |
主分类号 |
H03H11/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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