Apparatus and Methods for Adjusting Performance of Programmable Logic Devices

摘要

A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).