Circuit for protection of memory zones

摘要

A program execution CPU (1) exploits various peripherals (23,24) sharing the address bus (4) and the data bus (5). An execution RAM (21) and a mass storage nonvolatile memory (NVM) (22) connect to buses and peripherals. An interface circuit (6) is interposed between CPU and buses. The CPU sends instruction and data requests by providing instruction addresses and data addresses to interface circuit. A hardware monitor (7) intercepts the instruction addresses and data addresses. It verifies that certain cryptography algorithms or secret keys are only accessible by determined programs. The peripherals may be screen, keyboard, or another CPU. The programs are loaded into execution RAM when they are executed. The programs are stored in mass storage NVM when they are not being executed. An independent claim is included for computer system.