发明名称 |
Method and apparatus for testing semiconductor memory device and related testing methods |
摘要 |
A test method and apparatus for a semiconductor memory device is characterized by the sequentially programmed use of two test different modes. A first test mode tests at least signal line integrity for the semiconductor memory device by testing a merged set of bits line. The second test mode further tests at least signal line integrity after first separating the merged bits lines. Logical combination of test data derived from the first and second test modes are used to generate error detection signals. At least one bit line associated with a parity bit is preferable merged and separated in the foregoing approach.
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申请公布号 |
US7464309(B2) |
申请公布日期 |
2008.12.09 |
申请号 |
US20040006788 |
申请日期 |
2004.12.08 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
SEO SEONG-YOUNG |
分类号 |
G11C29/00;G11C7/00;G11C29/12 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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