发明名称 High performance serial bus testing methodology
摘要 According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.
申请公布号 US7464307(B2) 申请公布日期 2008.12.09
申请号 US20030396071 申请日期 2003.03.25
申请人 INTEL CORPORATION 发明人 NEJEDLO JAY J.;WIZNEROWICZ MIKE;ELLIS DAVID G.;GLASS RICHARD J.;MARTWICK ANDREW W.;SCHOENBORN THEODORE Z.
分类号 G01R31/28;G01R31/317;G01R31/3187;G06F11/00;G06F11/26;G06F13/00;G06F19/00;H04L1/24 主分类号 G01R31/28
代理机构 代理人
主权项
地址