发明名称 VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS
摘要 In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub- integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. In one embodiment the sub- integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation.
申请公布号 WO2008147928(A1) 申请公布日期 2008.12.04
申请号 WO2008US64605 申请日期 2008.05.22
申请人 KONDA, VENKAT 发明人 KONDA, VENKAT
分类号 H01L25/00 主分类号 H01L25/00
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