发明名称 |
WAFER LEVEL CHIP SCALE PACKAGE OF AN IMAGE SENSOR BY MEANS OF THROUGH HOLE INTERCONNECTION AND METHOD FOR MANUFACTURING THE SAME |
摘要 |
The present invention relates to a wafer level chip scale package of an image sensor by means of through hole interconnection and a method for manufacturing the same, in which through hole-interconnected electrodes, through holes filled with metals, are induced to the back side of a wafer substrate. In this structure, a length of wiring can be minimized to decrease a power loss and speed up signal transfer. A wafer level chip scale package of an image sensor by means of through hole interconnection in accordance with one embodiment of the present invention comprises: an image sensor for converting light from outside to an electrical signal, the image sensor being located on the front side of a wafer substrate; the electrode pads for outputting the electrical signal made in the image sensor, the electrode pads being located on the wafer substrate and extending near or into a dicing street; a through hole-interconnected electrode for transferring the electrical signal outputted from the electrode pads to the back side of the wafer substrate; and bumps on the through hole interconnected electrode. We call the technology in the present invention as "J-connection technology". |
申请公布号 |
WO2008143461(A2) |
申请公布日期 |
2008.11.27 |
申请号 |
WO2008KR02837 |
申请日期 |
2008.05.21 |
申请人 |
PARK, TAE-SEOK;KIM, YOUNG SUNG |
发明人 |
PARK, TAE-SEOK;KIM, YOUNG SUNG |
分类号 |
H01L21/60 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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