| 摘要 |
Methods and systems for coupling a 3D pipeline to a generic video processing unit (VPU) are disclosed. Aspects of one method may include concurrently accessing different portion of stored graphics data by the generic VPU and the 3D pipeline within a chip. The graphics data may be processed by the VPU and the 3D pipeline. The VPU may be able to perform, for example, vector processing and scalar processing. The vector processing may be performed on the graphics data by a plurality of pixel processors. The graphics data may be stored and/or accessed in a vector register file (VRF), which may comprise a plurality of banks. Graphics data may be stored as a plurality of vectors in each of the banks in the VRF. The graphics data may be stored and/or read a vector at a time by the VPU and the 3D pipeline. Each vector may comprise, for example, 512 bits.
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