| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a memory controller, an information processor and electronic equipment for reducing power consumption upon a writing operation or an erasing operation. <P>SOLUTION: This memory controller for performing access to a memory for performing access to data in response to a command input synchronously with a transfer clock synchronously with its internal clock is provided with: a clock output control part for controlling the output of the transfer clock; a write-in control part for issuing a write command to the memory, and for outputting write data synchronously with the transfer clock, and for controlling the write-in of the write data into the memory; and a busy detection part for detecting the busy state of the memory. When the busy state of the memory is detected by the busy detection part after the write command is issued, the clock output control part stops the supply of the transfer clock to the memory only in a predetermined first designated period, and thereafter starts the supply of the transfer clock. <P>COPYRIGHT: (C)2009,JPO&INPIT |
