SEMICONDUCTOR STORAGE DEVICE

摘要

A shared terminal receives an address signal and a data signal. An address-valid terminal receives an address-valid signal indicating that a signal supplied to the shared terminal is an address signal. An arbiter decides which should be given a priority, an external access request or an internal refresh request. The arbiter inhibits accepting of the internal refresh request in response to an event that both a chip enable signal and the address-valid signal reach respective effective levels (the external access request). The arbiter permits accepting of the internal refresh request in response to a completion of a read or write operation. As a result, in the semiconductor storage device having the shared terminal for receiving the address and data signals, any conflict can be prevented between a read or write operation and the refresh operation responsive to an internal refresh request, thereby preventing any malfunction.