发明名称 DIGITAL SIGNAL PROCESSOR INTERRUPT ACCELERATOR
摘要 A circuit arrangement reduces the number of interrupts to a DSP required to transfer digital samples between external I/O devices and a data memory, thus allowing the DSP to perform additional sample processing operations. An interrupt accelerator responds to I/O interrupts from an I/O device by pausing the DSP, transferring samples with the data memory, and tracking the number of samples transferred. When a predetermined number of samples have been transferred, the interrupt accelerator interrupts the DSP to perform a block transfer of samples in conjunction with sample processing.
申请公布号 KR100869898(B1) 申请公布日期 2008.11.24
申请号 KR20027014572 申请日期 2002.10.30
申请人 发明人
分类号 G06F13/24;G06F13/28 主分类号 G06F13/24
代理机构 代理人
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