发明名称 SYSTEM AND METHOD OF COMMUNICATION USING MULTI-PHASE CLOCK SIGNAL
摘要 A communication system and a communication method using multi-phase clock signals reduce a jitter noise and a delay time in a phase interpolator circuit by performing a coarse lock process of a clock signal in a transmitting device and a fine lock process in a receiving device. A communication system(1000) includes a transmitting device(1100) and a receiving device(1200). The transmitting device receives a bit lock detection signal from the receiving device, performs the coarse lock in response to the bit lock detection signal, generates a first clock signal of which phase is adaptively changed, and outputs the first clock signal and the first data. The receiving device performs a fine lock based on the bit lock detection signal and the first clock signal, generates the internal clock signal with the plurality of phase clocks, and samples the first data in response to the internal clock signal, and generates write data.
申请公布号 KR20080102007(A) 申请公布日期 2008.11.24
申请号 KR20070048254 申请日期 2007.05.17
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 JANG, YOUNG CHAN
分类号 H04L7/02 主分类号 H04L7/02
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