| 摘要 |
<p>The dummy gate pattern consisting of the conducting material is formed in the insulating layer between the memory cells and the capacitance for not only CFGY but also CFGXY can be improved. The interference effect between the adjacent word lines can be reduced and the program speed can be improved. The non-volatile memory is provided. The source select transistor is formed on the semiconductor substrate(200). The drain selection transistor and a plurality of memory cell(220) between drain selection transistors are formed. The dummy gate pattern(222) is formed between memory cells(222). The interference capacitor between adjacent word lines using the dummy gate pattern can be reduced and the interference effect can be improved.</p> |
