| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a hold-free register cell which is used for general purposes. <P>SOLUTION: The hold-free register cell 1 comprises: a multiplexer 11 which switches two input signals based upon a clock signal CK as a switching signal; a delay circuit 12 which delays the clock signal CK according to an output delay time of the multiplexer 11 and outputs the delayed signal as a clock signal CKd; and a latch circuit 13 which latches data output from the multiplexer 11 as the clock signal CKd output from the delay circuit 12 falls. The multiplexer 11 outputs a data input signal D when the clock signal CK is "1" which is a level before a data input edge, and outputs the output signal Q1 of the latch circuit when the clock signal CK is "0" which is a level after the data input edge. <P>COPYRIGHT: (C)2009,JPO&INPIT |
