| 摘要 |
<p>A driver for digital complementary signals applied to RAM modules, comprises a chain of series-connected delay cells each with differential signal inputs and differential signal outputs. The driver further comprises two sets of output stages, each output stage with a signal input, a single-ended signal output and an enable input. The signal outputs of the output stages in the first set are all connected to a first common differential driver output and the signal inputs of the output stages in the first set are connected to signal outputs of different ones of the delay cells or to a signal input of the first delay cell in the chain. Further, the signal outputs of the output stages in the second set are all connected to a second common differential driver output and the signal inputs of the output stages in the second set are each connected to a signal output of a different one of the delay cells or to a signal input of the first delay cell in the chain. The driver properties at the first and second common differential driver outputs are digitally programmable by selectively applying enable signals to the enable inputs of the output stages. Likewise, by digitally programming the enabling signals that are statically applied to the driver's output stages, the essential driver properties can be adjusted: driver strength, slew rate and delay time.</p> |
