发明名称 Semiconductor memory device having layout area reduced
摘要 A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplying a P well voltage is provided in a third metal interconnection layer. The metal supplying the N well voltage is formed using a metal in the first metal interconnection layer and thus does not require a piling region to the underlayer, and only a piling region to the underlayer of the metal for the P well voltage needs to be secured. Therefore, the length in the Y direction of a power feed cell can be reduced thereby reducing the layout area of the power feed cell.
申请公布号 US7453126(B2) 申请公布日期 2008.11.18
申请号 US20070797806 申请日期 2007.05.08
申请人 RENESAS TECHNOLOGY CORP. 发明人 ISHII YUICHIRO
分类号 H01L29/26;H01L29/94;H01L31/062;H01L31/113;H01L31/119 主分类号 H01L29/26
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