发明名称 Pll Circuit
摘要 A PLL circuit is disclosed that comprises a controlling unit that switches at a predetermined timing to enable/disable the phase difference signal supplied from the phase comparator to the low pass filter; and a resistor element that is disposed between a predetermined potential and a signal line for supplying the phase difference signal from the phase comparator to the low pass filter, when the phase difference signal is enabled, the oscillation circuit performing oscillation operation based on the voltage signal corresponding to the phase difference signal, when the phase difference signal is disabled, the low pass filter being supplied with the predetermined potential through the resistor element to allow the oscillation circuit to perform oscillation operation based on the voltage signal generated depending on the supplied predetermined potential.
申请公布号 US2008278248(A1) 申请公布日期 2008.11.13
申请号 US20050590644 申请日期 2005.02.14
申请人 SANYO ELECTRIC CO., LTD 发明人 KIMURA SYUJI;HASHIZUME TAKASHI
分类号 H03L7/099;H03L7/18;G06F1/04;H03C3/00;H03L7/093 主分类号 H03L7/099
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