| 摘要 |
<p>To provide a mechanism for controlling a substrate voltage and a power supply voltage for suppressing MOS transistor device fluctuation by a simple means and to simplify a testing step. Combinations of a plurality of power supply voltage values (VDD) and substrate voltage values (VBP, VBN) are set in ROMs (ROM1- ROM 7). At the time of performing chip test, drain current and operation speed tests are performed at first to MOS transistors (PT, NT) to be controlled, while the transistors are turned off, and device fluctuation is confirmed. Fuse circuits (FU0-FU1) program to select an ROM having an optimum combination of the power supply voltage value (VDD) and the substrate voltage values (VBP, VBN), corresponding to the status of device fluctuation. In the subsequent chip tests, optimum substrate voltages are determined by looking up an ROM table corresponding to a power supply voltage value inputted from the external.</p> |
