发明名称 |
METHODS FOR CONDUCTING DOUBLE-SIDE-BIASING OPERATIONS OF NAND MEMORY ARRAYS |
摘要 |
Methods are described for double-side-biasing of a NAND memory array device comprising a plurality of charge trapping memory cells for programming and erasing the NAND memory array device. A double-side-biasing method applies a bias voltage simultaneously on a first junction (a source region) and a second junction (a drain region) so that a left bit and a right bit in a charge trapping memory cell can be programmed in parallel or erased in parallel. Random (or selective) bit program and random (or selective) bit erase can be achieved by using a double-side-biasing method on a NAND memory array device for both data and code application. A first type of double-side-biasing method is to program the NAND array with a double-side-bias electron injection. A second type of double-side-biasing method is to erase the NAND array with a double-side-bias hole injection.
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申请公布号 |
US2008266980(A1) |
申请公布日期 |
2008.10.30 |
申请号 |
US20070741059 |
申请日期 |
2007.04.27 |
申请人 |
MACRONIX INTERNATIONAL CO., LTD. |
发明人 |
WU CHAO-I |
分类号 |
G11C11/34 |
主分类号 |
G11C11/34 |
代理机构 |
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代理人 |
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