| 摘要 |
PROBLEM TO BE SOLVED: To speed up processing by restraining a data transfer delay between a processor and a memory. SOLUTION: This vector processing apparatus comprises vector processors 3<SB>1</SB>, 3<SB>2</SB>, ..., 3<SB>n</SB>and memory control parts 4<SB>1</SB>, 4<SB>2</SB>, ..., 4<SB>m</SB>. Each of the vector processors 3<SB>1</SB>, 3<SB>2</SB>, ..., 3<SB>n</SB>has a memory access control part (a control information generating circuit 9) 33 generating control information on memory access based on instruction classification and instruction contents consisting of a base address, a distance and the number of elements, and port caches 36 switching the presence/absence of cache registration or/and a registration size based on the generated control information. Each of the memory control parts 4<SB>1</SB>, 4<SB>2</SB>, ..., 4<SB>m</SB>comprises bank caches 43 switching the presence/absence of cache registration or/and a registration size based on the generated control information, and memory banks 44 switching memory access units. COPYRIGHT: (C)2009,JPO&INPIT
|
