| 摘要 |
<p>A processing arrangement with a processor core (100) and a cache controller logic (102), as well as a first and a second memory block (104(1), 104(2)) in random access memory. The first memory block (104(1)) has a cache administration memory (104(1a) - 104(1c)). The second memory block (104(2)) has a cache memory (104(2a)). The cache memory (104(2a)) has a cache memory size that is set by cache management information stored in a cache control register (103) in the cache controller logic (102) as instructed by the processor core (100) while running a program or the cache control register (104(1 a) - 104(1c)) has a cache control register size that is set by the cache management information stored in the cache control register (103) as instructed by the processor core (100) while running the program, or both.</p> |
