Low latency communication using memory address translation

摘要

A high performance computer system has compute nodes interconnected by an inter-node communication network. The compute nodes include local packetized interconnects. Shared memory between compute nodes is emulated by tunneling packetized interconnect packets between the compute nodes. A memory region on one of the compute nodes is used as a window into a memory region in another compute node. Special registers may be provided to expedite remote operations on small amounts of data.