| 摘要 |
A system and method for identifying, for a selected signal, those signals whose value is relevantly determined based upon a value of the selected signal, where a set of signals to be examined is identified as those signals that satisfy one or more of the following criteria: (1) they are RTL load signals of the selected signal, (2) they are RTL load signals that are also in an analysis region, (3) they are RTL load signals within the analysis region that also contribute to a proof target, and/or 4) they are RTL load signals that contribute to the proof target. In one embodiment of the present invention the selected signal at a selected time step relevantly determines a target signal at an associated time step if one of the following items is true: (1) if the value of the selected signal at the selected time step changes (from 0 to 1 or from 1 to 0), the value of the target signal must change, or (2) if the value of the selected signal does not change, the value of the target signal at its associated time step cannot change regardless of how the rest of the inputs to the logic driving the target signal changes. Another embodiment of the present invention, the selected signal at the selected time step relevantly determines a target signal at an associated time step if the value of the selected signal at the selected time step were different then the value of the target signal at the associated time step would be different.
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