A SAW device package and a fabricating method thereof are provided to increase a yield in a package manufacturing process by reducing an influence on an internal pattern thereof. A via(210) is formed in a first wafer(200). A first pattern is formed on one surface of the first wafer. The first pattern is electrically connected with the via. A second pattern is formed on the other surface of the first wafer. A cap is formed to cover at least one of the first pattern and the second pattern. The first pattern and the second pattern include a pattern for composing an IDT(Inter-Digital Transducer). The via forming process includes a process for punching a via hole on the first wafer, and a process for filling up a conductive material in the via hole.
申请公布号
KR100862379(B1)
申请公布日期
2008.10.13
申请号
KR20070040219
申请日期
2007.04.25
申请人
SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人
KIM, HYUN HO;YIM, SOON GYU;HA, JOB;CHOI, SANG HYUN;PARK, SANG HEE