发明名称 PACKET PROCESSOR AND COMMUNICATION EQUIPMENT
摘要 <p><P>PROBLEM TO BE SOLVED: To obtain a packet processor for guaranteeing packet data by effectively utilizing the unused portion of a memory area allocated per one packet. <P>SOLUTION: The packet processor has a packet buffer 31 which has a plurality of memory areas for one packet storage for storing one variable-length packet, wherein each memory area for one packet storage has a packet storage area that can store a packet of the maximum length and an excess unused area, and each packet storage area is divided into a plurality of blocks, a control means for performing control to write and read a received packet to/from each block, and a block unit CRC checking part 60 for detecting the physical error of each block on the basis of data before being written to the block and data read from the block, wherein the control means uses a block set in an unused area in place of a block in which an error is detected to perform the subsequent buffering when the error is detected. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2008236309(A) 申请公布日期 2008.10.02
申请号 JP20070072199 申请日期 2007.03.20
申请人 FUJITSU LTD 发明人 KIDA TOSHIZANE;NOGUCHI TOSHIHIRO;YAMAJI KATSUICHI
分类号 H04L12/70;H04L1/00;H04L12/933;H04L13/08 主分类号 H04L12/70
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