| 摘要 |
PROBLEM TO BE SOLVED: To provide a technology for enabling a test using a scan path compression circuit in response to a power limitation in an LSI tester and a power supply noise limitation in a test environment. SOLUTION: A semiconductor integrated circuit comprises: the scan path circuit (2) including a plurality of scan paths; a pattern data generator (3) for supplying scan input pattern data to at least one of a plurality of the scan paths (2-1-2-n); an output compressor (4) for compressing output data from a plurality of the scan paths (2-1-2-n); and a scan path control circuit (5) for selecting the arbitrary scan paths among a plurality of the scan paths (2-1-2-n), and identifying a scan path route. The scan path control circuit (5) considers the scan paths included in the scan path route as selective scan paths, considers the scan paths excluded from the scan path route as nonselective scan paths, and inhibits the nonselective scan paths from being supplied with a clock. COPYRIGHT: (C)2009,JPO&INPIT
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