| 摘要 |
A push-pull pulse register circuit. The push-pull pulse register circuit includes a first logic inverter having first-inverter input and first-inverter output, a second logic inverter having second-inverter input and second-inverter output, a third logic inverter having third-inverter input and third-inverter output and configured to receive logic input data at the third-inverter input, a first logic gate having first-gate input, first-gate output, and first-gate control input, and a second logic gate having second-gate input, second-gate output, and second-gate control input. The third-inverter input is coupled to the first-gate input; the third-inverter output is coupled to the second-gate input; the second-inverter input is coupled to the second-gate output and the first-inverter output; the second-inverter output is coupled to the first-gate output and the first-inverter input; the first-gate control input is coupled to the second-gate control input; and the first-gate and the second-gate control inputs are configured to receive a clock pulse.
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