| 摘要 |
A DECISION FEEDBACK EQUALIZER FOR PROCESSING A DATA SIGNAL PROVIDES CONCURRENT EQUALIZER OUTPUTS FOR HARD DECISION DIRECTED AND SOFT DECISION DIRECTED MODES. THE JOINT ARCHITECTURE IN ACCORDANCE WITH THE PRESENT INVENTION TAKES ADVANTAGE OF THE FACT, HEREIN RECOGNIZED, THAT FOR EACH EQUALIZER OUTPUT SYMBOL SOFT DECISION BIT REPRESENTATION, A SUBSET OF THESE BITS CORRESPONDS TO THE HARD DECISION REPRESENTATION. AS A RESULT, THE INVENTION PERMITS THE CONCURRENT OUTPUT OF TWO DISTINCT MODES WITH ESSENTIALLY THE SAME HARDWARE AS A ONE OUTPUT EQUALIZER.FIGURE 1
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