| 摘要 |
PROBLEM TO BE SOLVED: To facilitate high-speed transfer even when there is a transfer delay difference between a clock signal line and a data signal line, and to carry out efficient transfer even when transfer requests are made simultaneously. SOLUTION: A serial bus configuration, in which a master module 1 and respective slave modules 2<SB>1</SB>to2<SB>3</SB>are connected by one-to-one connection, is constructed. A parallel-serial converter P/S for write access data and a serial-parallel converter S/P for read access data are arranged, and data transfer is carried out through respective data lines for the respective slave modules. When clock signalsϕ1toϕ3 with different frequencies are selected for each slave module by a multiplexer MUX, data transfer meeting the respective transfer speeds of the slave modules is carried out. In clock selection, a variable configuration by a register REG in the master module or a semifixed configuration by a digital switch DSW is set. COPYRIGHT: (C)2008,JPO&INPIT
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