发明名称 Clock distribution for interconnect structures
摘要 Some embodiments of the invention include an interconnect structure having a plurality of connector circuits to transfer messages among a number of devices. Each of the connector circuits includes a data transfer unit to transfer messages and a clock unit to provide timing to transfer the messages. The interconnect structure propagates a master clock signal serially through the clock units of the connector circuits to generate a number of different input clock signals. The timing provided by each of the clock units is based on the timing of one of the input clock signals. Other embodiments are described and claimed.
申请公布号 US7426632(B2) 申请公布日期 2008.09.16
申请号 US20050095289 申请日期 2005.03.31
申请人 INTEL CORPORATION 发明人 DENHAM MARTIN S.
分类号 G06F9/00;G06F15/177 主分类号 G06F9/00
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