| 摘要 |
There is provided a clock phase interpolator comprising a pair of output nodes, at least three complementary clock signal inputs, an equal plurality of current sources, and an equal plurality of clock switching sections. Each clock switching section is connected to switch, under the control of a complementary clock signal on a respective one of the complementary clock signal inputs, the current provided by a respective one of the current sources between the two output nodes. The current sources are controllable to provide interpolation between signals on the complementary clock signal inputs. Also provided is a clock phase interpolator comprising a pair of output nodes, two complementary clock signal inputs, an equal plurality of current sources, an equal plurality of clock switching sections. Each clock switching section is connected to switch, under the control of a complementary clock signal on a respective one of the complementary clock signal inputs, the current provided by a respective one of the current sources between the two output nodes. The current sources are controllable to provide interpolation between signals on the complementary clock signal inputs, and each load comprises an integrator.
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