发明名称 |
Intermediate Layout for Resolution Enhancement in Semiconductor Fabrication |
摘要 |
Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.
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申请公布号 |
US2008216047(A1) |
申请公布日期 |
2008.09.04 |
申请号 |
US20080099663 |
申请日期 |
2008.04.08 |
申请人 |
APRIO TECHNOLOLGIES, INC. |
发明人 |
WU SHAO-PO;WANG XIN;TANG HONGBO;HUNG MEG |
分类号 |
G06F17/50;G03F1/00;G03F1/36 |
主分类号 |
G06F17/50 |
代理机构 |
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