发明名称 |
SEMICONDUCTOR DEVICE AND DISPLAY ARRANGEMENT |
摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing a higher impedance due to long distance of power source wiring within a flip-chip that employs multi-pin outputs, and the voltage drop at both ends in the major side direction within the flip-chip. SOLUTION: A relay electrode region 108 is disposed in the mid-way of a power source wiring 105 of a single layer wiring substrate 103 packaged with the flip-chip 101 and an upper heat dissipation plate 107 having electric conductivity and thermal conductivity is arranged in the upper part of the flip-chip 101. The upper heat dissipation plate 107 and the relay electrode region 108 are electrically connected via a member 111 for connection. Then, the power source potential from a connector section 106 or ground potential is supplied to a pump electrode of the flip-chip 101 via power source wiring 105 and is also supplied to a bump electrode near the end of the flip-chip 101 on a more distant side via the upper heat dissipation plate 107 when viewed from the connector section 106. COPYRIGHT: (C)2008,JPO&INPIT
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申请公布号 |
JP2008203376(A) |
申请公布日期 |
2008.09.04 |
申请号 |
JP20070037259 |
申请日期 |
2007.02.19 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
YAMASHITA KENJI;KAGEYAMA HIROYUKI;MORIYAMA SEIICHI |
分类号 |
G09F9/00;H01J11/20;H01J11/46 |
主分类号 |
G09F9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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