| 摘要 |
<p>A semiconductor device and a manufacturing method thereof are provided to avoid signal propagation delay and to obtain a high-speed operation by reducing parasitic capacitance of a word line. A silicon crystal layer(21) is formed on an insulating layer(8). The silicon crystal layer includes a crystal lattice mismatch plane. A memory cell array unit is formed on the silicon crystal layer. The memory cell array unit includes a plurality of memory strings. Each of the memory strings includes a plurality of non-volatile memory cell transistors connected serially in a first direction. The memory strings are arranged in a second direction orthogonal to the first direction. The crystal lattice mismatch plane crosses the silicon crystal along the second direction without passing lower parts of the non-volatile memory cell transistors as viewed from a top of the silicon crystal layer, or crosses the silicon crystal along the first direction with passing lower parts of gates of the non-volatile memory cell transistors as viewed from the top of the silicon crystal layer.</p> |
