| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an array type processor which enables adjustment of cycle time for each configuration. <P>SOLUTION: The array type processor has: a data path section 10 in which a plurality of processor elements 11 are arranged in array-like; a state transition management section 12 which stores information to perform switching control of a data path; a delay adjustment circuit 13 which adjusts delay of an input clock signal based on information from the state transition management section to output to the data path section. The delay adjustment circuit 13 has a delay control information memory 14 and a programmable delay 15. The delay control information memory stores a plurality of pieces of delay control information, reads the delay control information with a configuration number from a state transition management section as an address and gives the delay control information to the programmable delay. The programmable delay makes the input clock signal delay only for the delay specified delay by the control information and outputs it to the data path section. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
