| 摘要 |
<p>A wafer-level package (10A; 10B; 10C; 10D; 10E; 10F; 10G; 10H; 101; 10J; 10K; 10L; 10M; 10N) includes a semiconductor wafer (11) having at least one semiconductor chip circuit forming region (12) each including a semiconductor chip circuit each provided with test chip terminals (13A) and non-test chip terminals (13B), at least one external connection terminal (14) , at least one redistribution trace (15) provided on the semiconductor wafer (11) , at least one testing member (16; 27; 33; 36), and an insulating material (17; 19, 20). A first end of the redistribution trace (15) is connected to one of the test chip terminals (13A) and a second end of said redistribution trace (15) is extended out to a position offset from the chip terminals (13, 13A, 13B). The testing member (16; 27; 33; 36) is provided in an outer region (18) of the semiconductor chip circuit forming region (12) , and the second end of the redistribution trace (15) is connected to the testing member (16; 27; 33; 36). <IMAGE></p> |
