INTER-COMMUNICATING MULTI MEMORY CHIP AND SYSTEM INCLUDING THE SAME

摘要

A multi-memory chip capable of performing inter-communication and a system including the same are provided to reduce latency by shortening a data transfer time among memories in the multi-memory chip stacking a multi-core CPU and a plurality of memories. A multi-memory chip(21) comprises a multi-core CPU(23) and a plurality of stacked memories respectively controlled by a corresponding CPU core. Data is directly exchanged among the memories. Each memory includes an I/O(Input/Output) sense amplifier and an I/O driver at a central part and/ an upper/lower ends for data transfer. A first memory receives a command for reading/transferring the data to second and third memories, and an address for reading the data from the first memory from a first CPU core corresponding to the first memory when the data is transferred from the first memory to the second and third memories.