| 摘要 |
A semiconductor device and a manufacturing method thereof are provided to lower a thickness of an interlayer dielectric for forming a metal line by reducing a step between a cell region and a peripheral circuit region. A lower electrode(224) is formed in a storage electrode hole within a first interlayer dielectric(210) of a cell region of a semiconductor substrate including the cell region and a peripheral circuit region. The lower electrode is exposed by etching the first interlayer dielectric. The exposed lower electrode is covered by forming a supporting layer on the semiconductor substrate. The first interlayer dielectric is exposed between the lower electrodes by etching the supporting layer. The lower electrode is exposed by removing the residual supporting layer. A capacitor(260) is formed in the cell region by forming a dielectric layer and an upper electrode(250) on the semiconductor substrate. A second interlayer dielectric(218) is formed in an upper part of the semiconductor substrate.
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