发明名称 Simulation system, simulation method and simulation program for verifying logic behavior of a semiconductor integrated circuit
摘要 A simulation system for verifying logic behavior of a semiconductor integrated circuit includes a reprogrammable semiconductor device having an interface circuit and a logic circuit; and an analyzing unit dividing a logic behavior of the semiconductor integrated circuit into a software-based first logic behavior and a hardware-based second logic behavior and generating circuit data of the interface circuit included in the first logic behavior that exhibits an input/output behavior and circuit data of the logic circuit that exhibits the second logic behavior.
申请公布号 US7418681(B2) 申请公布日期 2008.08.26
申请号 US20050193836 申请日期 2005.07.28
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 TAKEI TSUTOMU
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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