发明名称 DECODING CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To use an inexpensive memory as the line memory of a decoding circuit. <P>SOLUTION: A command comparator 102 separates compressed data into a first command that requires memory access and a second command that requires no memory access, and transmits them to caches 104 and 105. A decoder requests the memory read of decompressed data necessary for the decompression of the first command stored in the cache 104, and decodes the first command based on the decompressed data, and requests the memory write of the decompressed data acquired by decoding. An RAM access controller 106 controls the read and write of an RAM cache 107 and a line memory 108, and executes memory read and memory write corresponding to a request from the decoder 109. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008193146(A) 申请公布日期 2008.08.21
申请号 JP20070022234 申请日期 2007.01.31
申请人 CANON INC 发明人 SAKURAI TOSHIO
分类号 H03M7/30;H04N1/41;H04N19/00;H04N19/423;H04N19/44;H04N19/90 主分类号 H03M7/30
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