发明名称 SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREOF
摘要 A semiconductor memory device according to an embodiment comprises a memory cell array including first and second wiring line layers disposed sequentially above memory cells, the first wiring line layer including a first wiring line and a first dummy wiring line, and the second wiring line layer including a second wiring line and a second dummy wiring line, the second wiring line being disposed at the same position in the first direction as the first dummy wiring line, the second dummy wiring line being disposed at the same position in the first direction as the first wiring line, and during an access operation by a control circuit, the first and second wiring lines being electrically connected to at least one of the memory cells, and the first and second dummy wiring lines being fixed at a certain first potential.
申请公布号 US2016247571(A1) 申请公布日期 2016.08.25
申请号 US201514687177 申请日期 2015.04.15
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 TAKEKIDA Hideto
分类号 G11C16/06 主分类号 G11C16/06
代理机构 代理人
主权项 1. A semiconductor memory device, comprising: in the case that three directions intersecting each other are assumed to be a first direction, a second direction, and a third direction, a memory cell array including a plurality of memory cells and a first wiring line layer and second wiring line layer disposed sequentially above the memory cells in the third direction, the first wiring line layer including a first wiring line and a first dummy wiring line that are aligned in the first direction and have the second direction as a longer direction, and the second wiring line layer including a second wiring line and a second dummy wiring line that are aligned in the first direction and have the second direction as a longer direction; and a control circuit that controls an access operation above the memory cells, the second wiring line being disposed at the same position in the first direction as the first dummy wiring line, the second dummy wiring line being disposed at the same position in the first direction as the first wiring line, and during an access operation by the control circuit, the first wiring line and the second wiring line being electrically connected to at least one of the memory cells, and the first dummy wiring line and the second dummy wiring line being fixed at a certain first potential.
地址 Minato-ku JP